SY88983V Datasheet, PDF (1/9 Pages) Micrel Semiconductor – 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD

Micrel, Inc.
3.3V/5V 3.2Gbps CML
LOW-POWER LIMITING
POST AMPLIFIER w/TTL SD
SY88983V
SY88983V
FEATURES
DESCRIPTION
s Multi-Rate up to 3.2Gbps operation
s Wide gain-bandwidth product
• 38dB differential gain
• 2.2GHz 3dB bandwidth
s Low noise 50Ω CML data outputs
• 800mV_pp output swing
• 60ps edge rates
• 5ps_rms typ. random jitter
• 15ps_pp typ. deterministic jitter
s Chatter-free Signal Detect (SD) output
• 4.6dB electrical hysteresis
• OC-TTL output with internal 5kΩ pull-up resistor
s Programmable SD sensitivity using single external
resistor
s Internal 50Ω data input termination
s TTL EN input allows feedback from SD
s Wide operating range
• Single 3.3V ±10% or 5V ±10% power supply
• –40°C to +85°C industrial temperature range
s Available in tiny 10-pin MSOP (3mm) and 16-pin MLF™
(3mm × 3mm) packages
s NOT RECOMMENDED for New Designs!
APPLICATIONS
The SY88983V low-power limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88983V
quantizes these signals and outputs typically 800mV_pp
voltage-limited waveforms.
The SY88983V operates from a single +3.3V ±10% or
+5V ±10% power supply, over the industrial temperature of
–40°C to +85°C. With its wide bandwidth and high gain,
signals with data rates up to 3.2Gbps and as small as
10mV_pp can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
The SY88983V generates a signal detect (SD) open-
collector TTL output with internal 5kΩ pull-up resistor. A
programmable signal detect level set pin (SD_LVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SD_LVL
and de-asserts low otherwise. SD can be fed back to the
enable (EN) input to maintain output stability under a loss-
of-signal condition. EN de-asserts the true output signal
without removing the input signal. Typically, 4.6dB SD
hysteresis is provided to prevent chattering.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
s 1.25Gbps and 2.5Gbps Gigabit Ethernet
s 1.062Gbps and 2.125Gbps Fibre Channel
s 155Mbps, 622Mbps, 1.25Gbps and 2.5Gbps
SONET/SDH
s Gigabit interface converter (GBIC)
s Small form factor (SFF) and small form factor pluggable
(SFP) transceivers
s Parallel 10G Ethernet
s High-gain line driver and line receiver
TYPICAL PERFORMANCE
3.3V, 25°C, 10mV_PP Input
@2.5Gbps 2²³â€“1 PRBS, R_LOAD = 50Ω to V_CC
FUNCTIONAL BLOCK DIAGRAM
D_IN
50Ω
/D_IN
V_REF
V_CC
GND
Limiting
Amplifer
V_CC
—1.3V
2.8kΩ
SD_LVL
CML
Buffer
Level
Detect
TTL
Buffer
D_OUT
/D_OUT
EN
V_CC
5kΩ
OC-TTL
Buffer
SD
TIME (100ps/div.)
MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.
February 2005
1
M9999-020205
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