SY88843V Datasheet, PDF (1/11 Pages) Micrel Semiconductor – 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD

Micrel, Inc.
3.3V/5V 3.2Gbps CML LOW-POWER
LIMITING POST AMPLIFIER w/TTL SD
SY88843V
SY88843V
FEATURES
DESCRIPTION
s Multi-rate up to 3.2Gbps operation
s Wide gain-bandwidth product
• 38dB differential gain
• 2GHz 3dB bandwidth
s Low noise 50Ω CML data outputs
• 800mV_PP output swing
• 60ps edge rates
• 5ps_RMS typ. random jitter
• 15ps_PP typ. deterministic jitter
s Chatter-free, Signal-Detect (SD) output
• 4.6dB electrical hysteresis
• OC-TTL output with internal 4.75kΩ pull-up
resistor
s Programmable SD sensitivity using single external
resistor
s Internal 50Ω data input termination
s TTL EN input allows feedback from SD
s Wide operating range
• Single 3.3V ±10% or 5V ±10% power supply
• –40°C to +85°C industrial temperature range
s Available in tiny 10-pin EPAD-MSOP and
16-pin MLF™ packages
APPLICATIONS
s 1.25Gbps and 2.5Gbps Gigabit Ethernet
s 1.062Gbps and 2.125Gbps Fibre Channel
s 155Mbps, 622Mbps, 1.25Gbps, and 2.5Gbps SONET/
SDH
s Gigabit interface converter (GBIC)
s Small form factor (SFF) and small form factor
pluggable (SFP) transceivers
s Parallel 10G Ethernet
s High-gain line driver and line receiver
The SY88843V low-power limiting post amplifier is
designed for use in fiber-optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88843V
quantizes these signals and outputs typically 800mV_PP
voltage-limited waveforms.
The SY88843V operates from a single +3.3V ±10% or
+5V ±10% power supply, over an industrial temperature
range of –40°C to +85°C. With its wide bandwidth and high
gain, signals with data rates up to 3.2Gbps and as small as
10mVp-p can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
The SY88843V incorporates a signal detect (SD), open-
collector TTL output with internal 4.75kΩ pull-up resistor. A
programmable, loss-of-signal level set pin (SDLVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SDLVL
and de-asserts low otherwise. SD can be fed back to the
enable (EN) input to maintain output stability under a loss
of signal condition. EN asserts the true output signal without
removing the input signal. Typically 4.6dB SD hysteresis is
provided to prevent chattering.
Please see Micrel’s website at www.micrel.com for a
complete selection of optical module ICs. The following table
summarizes the differences between devices in Micrel’s
latest family of Limiting Amplifiers.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
Integrated 50Ω
Part Number Input Termination
SY88773V No
SY88823V No
SY88843V Yes
SY88973V Yes
LOS
or SD
LOS
SD
SD
LOS
Active LOW
or HIGH Enable
LOW
HIGH
HIGH
LOW
Table 1. Limiting Amplifiers Selection Guide
TYPICAL PERFORMANCE
3.3V, 25°C, 10mV_pp Input
@3.2Gbps 2³¹â€“1 PRBS, R_LOAD = 50Ω to V_CC
Micro LeadFrame and MLF are trademarks of Amkor Technology
M9999-110905
[e-mail] or [phone]
1
TIME (50ps/div.)
Rev.: C Amendment: /0
Issue Date: November 2005