SY87700 Datasheet, PDF (1/8 Pages) Micrel Semiconductor – CDR EVALUATION KIT

SY87700/SY87701 CDR
EVALUATION KIT
SY87700/SY87701
EVALUATION BOARD
FEATURES
DESCRIPTION
s 3.3V power supply:
Split V_CC = +2V, GND = 0V
V_EE = –1.3V for 3.3V
V_EE = –3V for 5.0V
s Simple switch configuration
s PECL signal outputs
s Simple RDIN+, RDIN– PECL inputs
s Simple REFCLK TTL input
s SY87700: Clock and data recovery from 32Mbps up
to 175Mbps NRZ data stream, clock generation from
32Mbps to 175Mbps
s SY87701: Clock and data recovery from 32Mbps up
to 1.25Gbps NRZ data stream, clock generation from
32Mbps to 1.25Gbps
The SY87700 and SY87701 Clock and Data Recovery
(CDR) chips are both high-performance ICs that are
designed to provide protocol-independent clock and data
recovery at any data rate between 32Mbps and 175Mbps
for the SY87700 and 32Mbps to 1.25Gbps for the SY87701.
This document provides design and implementation
information, as well as a detailed description of the SY87700/
701 evaluation board.
The evaluation board is intended to provide a convenient
test and evaluation platform for the SY87700/701 CDR
device. This board can be used for many types of jitter
tests, including SONET compliance of the SY87700/701,
as well as PLL characterization.
FUNCTIONAL BLOCK DIAGRAM
150 ps TTC*
150 ps TTC*
Scope
CH1
CH2
TRIG
CLKOUT
BERT Stack _DATAIN
DATAOUT–
CLKIN
J1
50Ω Term.
J4
J5
J2
50Ω Term.
PECL
PECL
V_CC +2V
LED ON - LOCK
LFIN
RDIN+ (PECL)
RDIN— (PECL)
SY87700
SY87701
RDOUT+
RDOUT—
RCLK+
RCLK—
PECL J12
PECL J11
PECL _J10
PECL J9
J6
250 ps TTC*
J3
50Ω Term.
TTL
REFCLK (TTL)
GND 0V
TCLK+
TCLK—
PECL J8
PECL J7
V_EE
Z_O = 50Ω
(—1.3V for 3.3V)
(—3V for 5.0V)
32 EP-TQFP
Pulse
Generator
*Note: TTC = HP / Agilent Transition Time Converter
150ps:HP15435A
2000ps: HP15438A
Spectrum
Analyzer
Figure 1. SY87700/SY87701 Evaluation Board and Test Set-Up
1
Rev.: A Amendment: /0
Issue Date: July 2002