SY69952A Datasheet, PDF (1/8 Pages) Micrel Semiconductor – OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER

OC-3/STS-3
CLOCK RECOVERING
TRANSCEIVER
SY69952A
FEATURES
DESCRIPTION
s A complete SONET/SDH/ATM compatible single chip
Transmitter and Receiver
s Seamless operation with PMC-Sierra PM5345, VLSI
VNS67200, IgT WAC-013-B/WAC-413-A and NEC
µPD98402 UNI Processors
s Supports clock and data recovery from 51.84 Mbit/s
or 155.52 Mbit/s NRZ or NRZI data stream
s 155.52MHz clock multiplication from 19.44MHz
source or 51.84MHz clock multiplication from
6.48MHz source
s Line Receiver Inputs: No external buffering needed
s Differential output buffering
s Link Status Indication
s Loop-back testing
s 100K ECL compatible I/O
s Single +5 volt power supply
s Available in 28-pin SOIC package
Micrel-Synergy's SY69952A contains fully integrated
transmitter and receiver functions designed to provide
clock recovery and generation for either 51.84Mbit/s OC/
STS-1 or 155.52Mbit/s OC/STS-3 SONET/SDH
(SY69952) and ATM applications.
On-chip clock generation is performed by a low-jitter
phase-locked loop (PLL) allowing use of 19.44MHz
reference for 155.52MHz generation or a 6.48MHz
reference for 51.84MHz generation. Clock recovery is
performed by synchronizing the on-chip VCO directly to
the incoming data stream.
Micrel-Synergy's circuit design techniques coupled with
ASSET™ bipolar technology result in ultra-fast
performance with low noise and low power dissipation.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
ROUT+
ROUT-
RIN+
RIN-
CD
TOUT+
TOUT-
LOOP
PLL2+
PLL2- MODE
PLL
RECEIVE
TRANSMIT
PLL
x8
RCLK+
RCLK-
RSER+
RSER-
LFI
TSER+
TSER-
TCLK+
TCLK-
ROUT+
ROUT-
RIN+
RIN-
MODE
VCC
CD
LOOP
REFCLK-
REFCLK+
TOUT-
TOUT+
PLL1+
PLL1-
1
28
2
27
3
26
4
25
5
24
6
23
7 _{TOP VIEW} 22
8
SOIC
21
9
20
10
19
11
18
12
17
13
16
14
15
RCLK-
RCLK+
RSER-
RSER+
LFI
VCC
VEE
VCC
TCLK-
TCLK+
TSER+
TSER-
PLL2+
PLL2-
REFCLK+
REFCLK-
PLL1+
PLL1-
Rev.: C
Amendment: /0
1
Issue Date: May 2000