SY69753L Datasheet, PDF (1/9 Pages) Micrel Semiconductor – 3.3V 125 MBPS 155 MBPS CLOCK AND DATA RECOVERY

Micrel
3.3V, 125Mbps 155Mbps
CLOCK and DATA RECOVERY
SY69753L
SY69753L
FEATURES
DESCRIPTION
s Industrial temperature range (–40°C to +85°C)
s 3.3V power supply
s SONET/SDH/ATM compatible
s Clock and data recovery for 125Mbps/155Mbps NRZ
data stream
s Two on-chip PLLs: one for clock generation and
another for clock recovery
s Selectable reference frequencies
s Differential PECL high-speed serial I/O
s Line receiver input: no external buffering needed
s Link fault indication
s 100k ECL compatible I/O
s Complies with Bellcore, ITU/CCITT and ANSI
specifications for OC-3 applications
s Available in 32-pin EPAD-TQFP
The SY69753L is a complete Clock Recovery and Data
Retiming integrated circuit for OC-3/STS-3 applications
at 155Mbps NRZ. The device is ideally suited for SONET/
SDH/ATM applications and other high-speed data
transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
The SY69753L also includes a link fault detection
circuit.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
APPLICATIONS
s Ethernet media converter
s SONET/SDH/ATM OC-3
s Proprietary architectures at 135Mbps to 180Mbps
BLOCK DIAGRAM
RDINP
(PECL)
RDINN
CD (PECL)
REFCLK
(TTL)
PLLR P/N
PHASE
DETECTOR
0
1
PHASE/
FREQUENCY
DETECTOR
CHARGE
PUMP
VCO
PHASE/
FREQUENCY
DETECTOR
CHARGE
PUMP
VCO
DIVIDER
BY 8, 10, 16, 20
DIVSEL 1/2
(TTL)
PLLS P/N
1
LINK FAULT
DETECTION
1
0
CLKSEL
(TTL)
RDOUTP
(PECL)
RDOUTN
RCLKP
(PECL)
RCLKN
LFIN
(TTL)
TCLKP
(PECL)
TCLKN
VCC
VCCA
VCCO
GND
Rev.: B Amendment: /2
Issue Date: September 2003