SY605 Datasheet, PDF (1/8 Pages) Micrel Semiconductor – 125MHz WRITE PROGRAMMABLE TIMING EDGE VERNIER

125MHz WRITE
PROGRAMMABLE
TIMING EDGE VERNIER
SY605
FEATURES
s True 125MHz retrigger rate
s Pin-compatible with Bt605
s 15ps delay resolution
s Less than ± 1 LSB timing accuracy
s Differential TRIGGER and delay WRITE inputs
s Delay spans from 4 to 40ns
s Compatible with 10KH ECL logic
s Lower power dissipation 350mW typical
s Available in 28-pin plastic (PLCC) or metal (MLCC)
J-lead package
BLOCK DIAGRAM
D0 - D7
WRITE
8
LATCH
VBB
8
DAC
I/V
+
PULSE
–
GEN
OUT
DESCRIPTION
Micrel-Synergy's SY605 is an ECL-compatible timing vernier
(delay generator) whose time delay is programmed via an 8-
bit code which is loaded via an independent "WRITE" input.
The SY605 is fabricated in Micrel-Synergy's proprietary
ASSET™ bipolar process.
This device can be retriggered at speeds up to 125MHz,
with a delay span as short as 4ns. At minimum span, the
resolution is 4ns/255 = 15.7ps per step. The delay span is
externally adjustable up to 40ns. The SY605 employs
differential TRIGGER and WRITE inputs, and produces a
differential OUTPUT pulse; all other control signals are single-
ended ECL. Edge delay is specified by an 8-bit input which is
loaded into the device with the WRITE signal. The output
pulse width will typically be 3.5ns.
The SY605 is commonly used in Automatic Test Equipment
to provide precise timing edge placement; it is also found in
many instrumentation and communications applications.
Micrel-Synergy's circuit design techniques coupled with
ASSET™ technology result in not only ultra-fast performance,
but allow device operation at lower power dissipation than
competing technologies. Outstanding reliability is achieved in
volume production.
PIN CONFIGURATION
CE
TRIG
D
FF
R
0 = STOP
1 = RUN
LINEAR
RAMP
GENERATOR
IEXT
25 24 23 22 21 20 19
D0 26
18 COMP2
D1 27
17
NC
D2 28
D3
1
D4
2
D5
3
TOP VIEW
PLCC
J28-1
16 NC
15
CE
14 COMP1
13 WRITE
D6
4
12
VBB
5 6 7 8 9 10 11
Rev.: E Amendment: /0
1
Issue Date: May, 1998