SY10H841L Datasheet, PDF (1/5 Pages) Micrel Semiconductor – 3.3V SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE

3.3V SINGLE SUPPLY QUAD
PECL-TO-TTL W/LATCHED
OUTPUT ENABLE
ClockWorks™
PRELIMINARY
SY10H841L
SY100H841L
FEATURES
s 3.3V power supply
s Translates positive ECL to TTL (PECL-to-TTL)
s 300ps pin-to-pin skew
s 500ps part-to-part skew
s Differential internal design for increased noise
immunity and stable threshold inputs
s VBB reference output
s Single supply
s Enable input
s Latch enable input
s Extra TTL and ECL power/ground pins to reduce
cross-talk/noise
s High drive capability: 24mA each output
s Fully compatible with industry standard 10K, 100K
I/O levels
s Available in 16-pin SOIC package
DESCRIPTION
The SY10/100H841L are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 20pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled low by the internal pull-
downs) the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H841 solves several clock distribution
problems such as minimizing skew (300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
PIN CONFIGURATION
BLOCK DIAGRAM
VBB
D
D
LEN
DQ
EN
LEN ¹
16 _Q3
EN ²
15 _GT
Q0
GE ³
14 _Q2
VE ⁴ SOIC ¹³ VT
D ^{5 Z16-1 12} VT
D6
11 _Q1
Q1
VBB ⁷
10 _GT
GT ⁸
9 _Q0
Q2
PIN NAMES
Q3
Pin
Function
GT
TTL Ground (0V)
VT
TTL VCC (+3.3V)
VE
ECL VCC (+3.3V)
GE
ECL Ground (0V)
D, D
Signal Input (PECL)
VBB
VBB Reference Output (PECL)
Q0 - Q3
Signal Outputs (TTL)
EN
Enable Input (PECL)
LEN
Latch Enable Input
Rev.: C Amendment: /0
1
Issue Date: May, 1999