SY10H641_06 Datasheet, PDF (1/6 Pages) Micrel Semiconductor – SINGLE SUPPLY 1:9 PECL-TO-TTL

Micrel, Inc.
SINGLE SUPPLY 1:9
PECL-TO-TTL
Precision Edge^®
Precision E_SSd_YY1g¹⁰e^{00HH®664411}
SY10H641
SY100H641
FEATURES
s Input frequencies up to 135MHz
s PECL-to-TTL version of popular ECLinPS E111
s Guaranteed low skew specification
s Latched input
s Differential internal design
s VBB output VECL for single-ended operation
s Single +5V supply
s Reset/enable
s Extra TTL and ECL power/ground pins
s Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s Available in 28-pin PLCC package
BLOCK DIAGRAM
TTL Outputs
Q0
Precision Edge^®
DESCRIPTION
The SY10/100H641 are single supply, low skew
translating 1:9 clock drivers. Devices in the Micrel H600
translator series utilize the 28-lead PLCC for optimal
power pinning, signal flow-through and electrical
performance.
The devices feature a 24mA TTL output stage with
AC performance specified into a 50pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled LOW by the internal pull-
downs), the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
PIN NAMES
Q1
Q2
PECL Input
Q3
D
DQ
Q4
D
VBB
Q5
LEN
EN
Q6
Pin
GT
VT
VE
GE
D, D
VBB
Q0 - Q8
EN
LEN
Function
TTL Ground (0V)
TTL VCC (+5.0V)
ECL VCC (+5.0V)
ECL Ground (0V)
Signal Input (PECL)
VBB Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Latch Enable Input (PECL)
Q7
Q8
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M9999-032906
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1
Rev.: E
Amendment: /0
Issue Date: March 2006