SY10H641A Datasheet, PDF (1/5 Pages) Micrel Semiconductor – SINGLE SUPPLY 1:9 PECL-TO-TTL

SY NERGY
SEMICONDUCTOR
SINGLE SUPPLY 1:9
PECL-TO-TTL
ClockWorks™
ClockW_So^SYr^Y1k₀₁₀₀s_HH™_664411AA
SY10H641A
SY100H641A
FEATURES
DESCRIPTION
s Input frequencies up to 80MHz
s PECL-to-TTL version of popular ECLinPS E111
s Guaranteed low skew specification
s Latched input
s Differential ECL internal design
s VBB output for single-ended operation
s Single +5V supply
s Reset/enable
s Extra TTL and ECL power/ground pins
s Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s ESD protection of 2000V
s Fully compatible with Motorola MC10H641/100H641
s Available in 28-pin PLCC package
The SY10/100H641A are single supply, low skew
translating 1:9 clock drivers. Devices in the Synergy H600
translator series utilize the 28-lead PLCC for optimal
power pinning, signal flow-through and electrical
performance.
The devices feature a 24mA TTL output stage with
AC performance specified into a 50pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled LOW by the internal pull-
downs), the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
TTL Outputs
PIN CONFIGURATION
PECL Input
Q0
25 24 23 22 21 20 19
GT
26
18
VBB
Q1
Q5
27
17
D
VT
28
16
D
Q4
1
TOP VIEW
PLCC
15
VE
Q2
VT
2
14 _LEN
Q3 3
13
GE
GT
4
12 _EN
5 6 7 8 9 10 11
Q3
D
DQ
D
Q4
PIN NAMES
VBB
LEN
EN
© 1999 Micrel-Synergy
Q5
Pin
Function
GT
TTL Ground (0V)
VT
TTL VCC (+5.0V)
Q6
VE
ECL VCC (+5.0V)
GE
ECL Ground (0V)
D, D
Signal Input (PECL)
Q7
VBB
VBB Reference Output (PECL)
Q0 - Q8
Signal Outputs (TTL)
EN
Enable Input (PECL)
Q8
LEN
Latch Enable Input (PECL)
5-356
Rev.: D
Amendment: /0
Issue Date: February, 1999