SY10H603 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 9-BIT LATCHED ECL-TO-TTL

9-BIT LATCHED
ECL-TO-TTL
SY10H603
SY100H603
FEATURES
s 9-bit ideal for byte-parity applications
s 3-state TTL outputs
s Flow-through configuration
s Extra TTL and ECL power/ground pins to minimize
switching noise
s Dual supply
s 6.0ns max. delay into 50pF, 12ns into 200pF (all
outputs switching)
s PNP TTL inputs for low loading
s Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s Fully compatible with Motorola MC10H/100H603
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H603 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. Latching is controlled by Latch Enable
(LEN) and Master Reset (MR) resets the latches. A HIGH
on OEECL sends the outputs into the high impedance
state. All control inputs are ECL level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
PIN CONFIGURATION
BLOCK DIAGRAM
OEECL
D0
D1
D2
D3
ECL
D4
D5
D6
D7
D8
LEN
MR
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
25 24 23 22 21 20 19
Q4 26
18
D8
Q0
Q3 27
VCCT 28
17
D7
16
VCCE
Q2
1
TOP VIEW
15
D6
PLCC
Q1
GND 2
14
D5
Q1
3
13
D4
Q0
4
12
D3
Q2
5 6 7 8 9 10 11
Q3
Q4
TTL
PIN NAMES
Q5
Pin
Function
GND
TTL Ground (0V)
Q6
VCCE
ECL VCC (0V)
VCCT
TTL Supply (+5.0V)
Q7
VEE
ECL Supply (–5.2/–4.5V)
D0–D8
Data Inputs (ECL)
Q0–Q8
Data Outputs (TTL)
Q8
OEECL
3-state Control (ECL)
LEN
Latch Enable (ECL)
MR
Master Reset (ECL)
Rev.: D
Amendment: /0
1
Issue Date: April, 1998