SY10H602_06 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 9-BIT LATCHED TTL-TO-ECL

Micrel, Inc.
9-BIT LATCHED
TTL-TO-ECL
SY10H602
SY1^S0^YH¹⁰6⁰0^H2⁶⁰²
SY100H602
FEATURES
s 9-bit ideal for byte-parity applications
s Flow-through configuration
s Extra TTL and ECL power/ground pins to minimize
switching noise
s Dual supply
s 3.5ns max. D to Q
s PNP TTL inputs for low loading
s Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s Fully compatible with MC10H/100H602
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H602 are 9-bit, dual supply TTL-to-ECL
translators with latches. Devices in the Micrel 9-bit
translator series utilize the 28-lead PLCC for optimal
power pinning, signal flow-through and electrical
performance.
The H602 features D-type latches. Latching is
controlled by Latch Enable (LEN), while the Master Reset
input resets the latches. A post-latch logic enable is also
provided (ENECL), allowing control of the output state
without destroying latch data. All control inputs are ECL
level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
ENECL
D0
D1
D2
D3
TTL
D4
D5
D6
D7
D8
LEN
MR
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
PIN NAMES
Q0
Q1
Q2
Q3
Q4
ECL
Pin
GND
VCCE
VCCO
VCCT
VEE
D0–D8
Q0–Q8
ENECL
LEN
MR
Function
TTL Ground (0V)
ECL VCC (0V)
ECL VCC (0V) — Outputs
TTL Supply (+5.0V)
ECL Supply (–5.2/–4.5V)
Data Inputs (TTL)
Data Outputs (ECL)
Enable Control (ECL)
Latch Enable (ECL)
Master Reset (ECL)
Q5
Q6
Q7
Q8
M9999-032906
[e-mail] or [phone]
1
Rev.: E
Amendment: /0
Issue Date: March 2006