SY10H602 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 9-BIT LATCHED

9-BIT LATCHED
TTL-TO-ECL
SY10H602
SY100H602
FEATURES
s 9-bit ideal for byte-parity applications
s Flow-through configuration
s Extra TTL and ECL power/ground pins to minimize
switching noise
s Dual supply
s 3.5ns max. D to Q
s PNP TTL inputs for low loading
s Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s Fully compatible with Motorola MC10H/100H602
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H602 are 9-bit, dual supply TTL-to-ECL
translators with latches. Devices in the Micrel-Synergy
9-bit translator series utilize the 28-lead PLCC for optimal
power pinning, signal flow-through and electrical
performance.
The H602 features D-type latches. Latching is
controlled by Latch Enable (LEN), while the Master Reset
input resets the latches. A post-latch logic enable is also
provided (ENECL), allowing control of the output state
without destroying latch data. All control inputs are ECL
level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
PIN CONFIGURATION
ENECL
D0
D1
D2
D3
TTL
D4
D5
D6
D7
D8
LEN
MR
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
Q0
Q1
Q2
Q3
Q4
ECL
D6
D7
D8
GND
MR
LEN
ENECL
25 24 23 22 21 20 19
26
18
27
17
28
16
1
TOP VIEW
15
PLCC
2
14
3
13
4
12
5 6 7 8 9 10 11
Q0
Q1
VCCE
VCCO
Q2
VCCO
Q3
Q5
PIN NAMES
Pin
Function
Q6
GND
TTL Ground (0V)
VCCE
ECL VCC (0V)
Q7
VCCO
ECL VCC (0V) — Outputs
VCCT
TTL Supply (+5.0V)
Q8
VEE
ECL Supply (–5.2/–4.5V)
D0–D8
Data Inputs (TTL)
Q0–Q8
Data Outputs (ECL)
ENECL
Enable Control (ECL)
LEN
Latch Enable (ECL)
MR
Master Reset (ECL)
Rev.: D
Amendment: /0
1
Issue Date: March, 1998