SY10H601 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE

9-BIT ECL-TO-TTL
WITH 3-STATE ENABLE
SY10H601
SY100H601
FEATURES
s 9-bit ideal for byte-parity applications
s 3-state TTL outputs
s Flow-through configuration
s Extra TTL and ECL power/ground pins to minimize
switching noise
s ECL and TTL 3-state control inputs
s 4.8ns max. delay into 50pF, 9.6ns into 200pF (all
outputs switching)
s PNP TTL inputs for low loading
s Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s Fully compatible with Motorola MC10H/100H601
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H601 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. For the 3-state output disable, both
ECL and TTL control inputs are provided, allowing
maximum design flexibility.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
PIN CONFIGURATION
OEECL
OETTL
D0
D1
D2
D3
ECL
D4
D5
D6
D7
D8
25 24 23 22 21 20 19
Q0
Q4
26
18
D8
Q3
27
17
D7
Q1
VCCT
28
Q2
1
TOP VIEW
PLCC
16
VCCE
15
D6
GND 2
14
D5
Q2
Q1
3
13
D4
Q0
4
12
D3
Q3
5 6 7 8 9 10 11
Q4
TTL
Q5
PIN NAMES
Q6
Pin
Function
GND
TTL Ground (0V)
Q7
VCCE
ECL VCC (0V)
Q8
VCCT
TTL Supply (+5.0V)
VEE
ECL Supply (–5.2/–4.5V)
D0–D8
Data Inputs (ECL)
Q0–Q8
Data Outputs (TTL)
OEECL
3-State Control (ECL)
OETTL
3-State Control (TTL)
Rev.: D Amendment: /0
1
Issue Date: February, 1998