SY10H351 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – QUAD TTL/NMOS-to-PECL TRANSLATOR

QUAD TTL/NMOS-to-PECL
TRANSLATOR
SY10H351
FINAL
FEATURES
DESCRIPTION
s Single 5V power supply
s All V_CC pins isolated on chip
s Differentially drive balanced lines
s t_pd 1.3ns typical
s Fully compatible with ON Semiconductor MC10H351
s Available in 20-pin PLCC package
The SY10H351 is a quad translator for interfacing data
between a saturated logic selection and the PECL section
of digital systems when only a +5.0V V_DC power supply
is available. The SY10H351 has TTL/NMOS compatible
inputs and PECL complementary open-emitter outputs
that allow use as an inverting/non-inverting translator or
as a differential line driver. When the common strobe
input is at a low logic level, it forces all true outputs to
the PECL low logic state (≈ +3.2V) and all inverting
outputs to the PECL high logic state (≈ 4.1V).
The SY10H351 can also be used with the SY10H350
to transmit and receive TTL/NMOS information
differentially via balanced twisted pair lines.
BLOCK DIAGRAM
PIN CONFIGURATION
D1 7
D0 8
D3 12
D2 14
COMMON 9
STROBE
1 /Q1
2 Q1
5 /Q0
4 Q0
16 /Q3
17 Q3
19 /Q2
18 Q2
V_CC (+5 V_DC) = Pins 6, 11, 15, 20;
GND = Pin 10
18 17 16 15 14
/Q2 19
VCCE 20
/Q1 ₁
Q1 2
NC 3
Top View
PLCC
J20-1
13 NC
12 D3
11 _VCCT
10 GND
9 Common Strobe
456 7 8
PIN NAMES
Pin
D0 – D3
Q0 – Q3
/Q0 – /Q3
VCC1
VCCE
VCCT
VCC2
Common Strobe
GND
1
Function
Inputs
Outputs
Inverted outputs
PECL V_CC (5.0V)
PECL V_CC (5.0V)
TTL V_CC (5.0V)
PECL V_CC (5.0V)
Common Strobe
Ground
Rev.: A Amendment: /1
Issue Date: August 2000