SY10EP51V_09 Datasheet, PDF (1/8 Pages) Micrel Semiconductor – 5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK

Micrel, Inc.
5V/3.3V D FLIP-FLOP WITH RESET
AND DIFFERENTIAL CLOCK
ECL Pro^®
EC^SL^Y1P^0Er^Po^5®1V
SY10EP51V
FEATURES
■ 3.3V and 5V power supply options
■ 320ps typical propagation delay
■ Maximum frequency > 3GHz typical
■ 75KΩ internal input pulldown resistor
■ Transistor count: 143
■ Available in 8-Pin (3mmx3mm) MSOP, SOIC and
MLF^® (2mmx2mm) packages
ECL Pro^®
DESCRIPTION
The SY10EP51V is a D flip-flop with reset and
differential clock. The device is pin and functionally
equivalent to the EL51 device.
The reset input is an asynchronous, level triggered
signal. Data enters the master portion of the flip-flop
when CLK is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the CLK.
The differential clock inputs of the EP51V allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to
maintain stability under open input conditions. When left
open, the CLK input will be pulled down to V_EE and the
/CLK input will be biased a V_CC/2.
PIN NAMES
Pin
CLK, /CLK
RESET
D
Q, /Q
V_CC
V_EE
Function
ECL Clock Inputs
ECL Asynchronous Reset
ECL Data Input
ECL Data Outputs
Positive Supply
Negative, 0 Supply
TRUTH TABLE
D
RESET
CLK
Q
L
L
Z
L
H
L
Z
H
X
H
X
L
Z = LOW to HIGH Transition
ECL Pro is a registered trademark of Micrel, Inc.
M9999-060409
[e-mail] or [phone]
1
Rev.: E Amendment: /0
Issue Date: June 2009