SY10ELT23_03 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR

DUAL DIFFERENTIAL
PECL-to-TTL
TRANSLATOR
Precision Edge™
SY10ELT23
SY100ELT23
FINAL
FEATURES
s 3.0ns typical propagation delay
s <500ps typical output-to-output skew
s Differential PECL inputs
s 24mA TTL outputs
s Flow-through pinouts
s Available in 8-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
D0 1
D0 2
PECL
D1 3
D1 4
8 VCC
7 Q0
TTL
6 Q1
5 GND
SOIC
TOP VIEW
Precision Edge™
DESCRIPTION
The SY10/100ELT23 are dual differential PECL-to-TTL
translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and the low skew dual gate design
of the ELT23 makes it ideal for applications which require
the translation of a clock and a data signal.
The ELT23 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN NAMES
Pin
Qn
Dn
VCC
GND
Function
TTL Outputs
Differential PECL Inputs
+5.0V Supply
Ground
Precision Edge is a trademark of Micrel, Inc.
1
Rev.: I
Amendment: 0
Issue Date: February 2003