SY10ELT22_08 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR

Micrel, Inc.
DUAL TTL-to-DIFFERENTIAL
PECL TRANSLATOR
SY10ELT22
SY1^S0^YE¹L⁰⁰T^E2^L2^T22
SY100ELT22
FEATURES
s 300ps typical propagation delay
s <100ps output-to-output skew
s Differential PECL outputs
s PNP TTL inputs for minimal loading
s Flow-through pinouts
s Available in 8-pin SOIC package
DESCRIPTION
The SY10/100ELT22 are dual TTL-to-differential PECL
translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and the low skew, dual gate design
of the ELT22 makes it ideal for applications which require
the tranlation of a clock and a data signal.
The ELT22 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN NAMES
Pin
Qn
Dn
VCC
GND
Function
Differential PECL Outputs
TTL Inputs
+5.0V Supply
Ground
M9999-052108
[e-mail] or [phone]
1
Rev.: H Amendment: /0
Issue Date: May 2008