SY10ELT22 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR

DUAL TTL-to-DIFFERENTIAL
PECL TRANSLATOR
SY10ELT22
SY100ELT22
FEATURES
s 300ps typical propagation delay
s <100ps output-to-output skew
s Differential PECL outputs
s PNP TTL inputs for minimal loading
s Flow-through pinouts
s Available in 8-pin SOIC package
DESCRIPTION
The SY10/100ELT22 are dual TTL-to-differential PECL
translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and the low skew, dual gate design
of the ELT22 makes it ideal for applications which require
the tranlation of a clock and a data signal.
The ELT22 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
Q0 1
Q0 2
PECL
Q1 3
Q1 4
8 VCC
7 D0
TTL
6 D1
5 GND
SOIC
TOP VIEW
PIN NAMES
Pin
Qn
Dn
VCC
GND
Function
Differential PECL Outputs
TTL Inputs
+5.0V Supply
Ground
Rev.: F Amendment: /0
1
Issue Date: January, 1999