SY10ELT21_07 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – DIFFERENTIAL PECL-to-TTL TRANSLATOR

Micrel, Inc.
FEATURES
„ 2.5ns typical propagation delay
„ Low power
„ Differential PECL inputs
„ 24mA TTL outputs
„ Flow-through pinouts
„ Available in 8-pin SOIC package
DIFFERENTIAL
PECL-to-TTL
TRANSLATOR
Precison Edge^®
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SY10ELT21
SY100ELT21
Precision Edge^®
DESCRIPTION
The SY10/100ELT21 are single differential PECL-to-
TTL translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and low skew single gate design
make the ELT21 ideal for applications that require the
translation of a clock or data signal where minimal space,
low power, and low cost are critical.
The V_BB output allow differential single-ended, or AC-
coupled interface to the device. If used, the V_BB output
should be bypassed to V_CC with a 0.01µF capacitor.
The ELT21 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN NAMES
Pin
Q
D, /D
V_CC
V_BB
GND
Function
TTL Output
Differential PECL Inputs
+5.0V Supply
Reference Output
Ground
Precision Edge is a registered trademark of Micrel, Inc.
M9999-031506
[e-mail] or [phone]
1
Rev.: C Amendment: /0
Issue Date: March 2006