SY10ELT21 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – DIFFERENTIAL PECL-to-TTL TRANSLATOR

FEATURES
s 2.5ns typical propagation delay
s Low power
s Differential PECL inputs
s 24mA TTL outputs
s Flow-through pinouts
s Available in 8-pin SOIC package
DIFFERENTIAL
PECL-to-TTL
TRANSLATOR
ClockWorks™
SY10ELT21
SY100ELT21
DESCRIPTION
The SY10/100ELT21 are single differential PECL-to-
TTL translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and low skew single gate design
make the ELT21 ideal for applications that require the
translation of a clock or data signal where minimal space,
low power, and low cost are critical.
The V_BB output allow differential single-ended, or AC-
coupled interface to the device. If used, the V_BB output
should be bypassed to V_CC with a 0.01µF capacitor.
The ELT21 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
NC 1
D2
PECL
D3
V_BB 4
8 V_CC
TTL _{7 Q}
6 NC
5 GND
SOIC
TOP VIEW
PIN NAMES
Pin
Q
D, /D
V_CC
V_BB
GND
Function
TTL Output
Differential PECL Inputs
+5.0V Supply
Reference Output
Ground
Rev.: B Amendment: /0
1
Issue Date: April 2000