SY10EL35 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – JK FLIP-FLOP

JK FLIP-FLOP
SY10EL35
SY100EL35
FEATURES
s 525ps propagation delay
s 2.2GHz toggle frequency
s High bandwidth output transistions
s Internal 75KΩ input pull-down resistors
s Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL35 are high-speed JK Flip-Flops. The
J/K data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave and,
thus, the outputs, upon a positive transition of the clock.
The reset pin is asynchronous and is activated with a
logic HIGH.
PIN CONFIGURATION/BLOCK DIAGRAM
J1
K2
CLK ₃
R4
J
K
R
8 VCC
7Q
6Q
5 VEE
SOIC
TOP VIEW
TRUTH TABLE⁽¹⁾
J
K
R
L
L
L
L
H
L
H
L
L
H
H
L
X
X
H
NOTE:
1. Z = LOW-to-HIGH transition.
CLK
Z
Z
Z
Z
X
Qn+1
Qn
L
H
Qn
L
Rev.: E Amendment: /0
1
Issue Date: August, 1998