SY10EL34_11 Datasheet, PDF (1/7 Pages) Micrel Semiconductor – 5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip

SY10EL34/L
SY100EL34/L
5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip
Precision Edge^®
General Description
The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock
generation chips designed explicitly for low-skew clock
generation applications. The internal dividers are
synchronous to each other; therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V_BB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V_BB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor. The
V_BB output is designed to act as the switching reference for
the input of the EL34/L under single-ended input
conditions. As a result, this pin can only source/ sink up to
0.5mA of current.
The common enable ( EN ) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal
clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the
falling edge of the divider stages. The internal enable flip-
flop is clocked on the falling edge of the input clock;
therefore, all associated specification limits are referenced
to the negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
Precision Edge^®
• 3.3V and 5V power supply options
• 50ps output-to-output skew
• Synchronous enable/disable
• Master Reset for synchronization
• Internal 75KΩ input pull-down resistors
• Available in 16-pin SOIC package
Pin Description
Pin Name Pin Function
CLK
Differential clock inputs.
EN
Synchronous enable.
MR
Master reset.
V_BB
Reference output.
Q₀
Differential ÷2 outputs.
Q₁
Differential ÷4 outputs.
Q₂
Differential ÷8 outputs.
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax + 1 [phone] • http://www.micrel.com
December 2011
M9999-120611-I
[e-mail] or [phone]