SY10EL33 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 5V/3.3V ÷ 4 DIVIDER

5V/3.3V ÷ 4 DIVIDER
ClockWorks™
SY10EL33/L
SY100EL33/L
FEATURES
s 3.3V and 5V power supply options
s 650ps propagation delay
s 4.0GHz toggle frequency
s High bandwidth output transistions
s Internal 75KΩ input pull-down resistors
s Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL33/L are integrated ÷4 dividers. The
differential clock inputs and the VBB allow a differential,
single-ended or AC-coupled interface to the device. If
used, the VBB output should be bypassed to ground with
a 0.01µF capacitor. Also note that the VBB is designed to
be used as an input bias on the EL33/L only; the VBB
output has limited current sink and source capability.
The reset pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the reset input allows for the
synchronization of multiple EL33/Ls in a system.
PIN CONFIGURATION/BLOCK DIAGRAM
Reset ₁
CLK ₂
CLK ₃
VBB ₄
8 VCC
R
7Q
÷4
6Q
5 _VEE
SOIC
TOP VIEW
PIN NAMES
Pin
CLK
Reset
VBB
Q
Function
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Rev.: E Amendment: /1
1
Issue Date: August 2000