SY10EL15 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – 1:4 CLOCK DISTRIBUTION

Micrel, Inc.
1:4 CLOCK
DISTRIBUTION
Precision Edge^®
Precision _SE^SYd^Y110g⁰⁰e^EE®LL1155
SY10EL15
SY100EL15
FEATURES
s 50ps output-to-output skew
s Synchronous enable/disable
s Multiplexed clock input
s 75KΩ internal input pull-down resistors
s Available in 16-pin SOIC package
Precision Edge^®
DESCRIPTION
The SY10/100EL15 are low skew 1:4 clock distribution
chips designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the VBB output should be connected
to the CLK input and bypassed to VCC via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions, as a result this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
Precision Edge is a registered trademark of Micrel, Inc.
M9999-031006
[e-mail] or [phone]
11
Rev.: H
Amendment: /0
Issue Date: March 2006