SY10E451_06 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 6-BIT REGISTER DIFFERENTIAL DATA CLOCK

Micrel, Inc.
6-BIT REGISTER
DIFFERENTIAL DATA CLOCK
SY10E451
SY1^S0^YE¹⁰4⁰5^E1⁴⁵¹
SY100E451
FEATURES
s 1100MHz min. toggle frequency
s Extended 100E V_EE range of –4.2V to –5.5V
s Differential inputs: data and clock
s V_BB output for single-ended use
s Asynchronous Master Reset
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E451
s Available in 28-pin PLCC package
BLOCK DIAGRAM
D₀
/D₀
D₁
/D₁
D₂
/D₂
D₃
/D₃
D₄
/D₄
D₅
/D₅
CLK
/CLK
MR
V_BB
D
Q₀
R
D
Q₁
R
D
Q₂
R
D
Q₃
R
D
Q₄
R
D
Q₅
R
DESCRIPTION
The SY10/100E451 offer six D-type flip-flops with single-
ended outputs and differential data and clock inputs,
designed for use in new, high-performance ECL systems.
The registers are triggered by the rising edge of the CLK
input.
A logic HIGH on the Master Reset (MR) input resets all
outputs to a logic LOW. The V_BB output is provided for use
as a reference voltage for single-ended reception of ECL
signals to that device only. When used for this purpose, it
is recommended that V_BB is decoupled to V_CC via a 0.01µF
capacitor.
PIN NAMES
Pin
D0–D5
/D0–/D5
CLK
/CLK
Q0–Q5
MR
V_BB
V_CCO
Function
+ Data Input
– Data Input
+ Clock Input
– Clock Input
Data Outputs
Master Reset Input
V_BB Output
V_CC to Output
M9999-032206
[e-mail] or [phone]
1
Rev.: G
Amendment: /0
Issue Date: March 2006