SY10E451 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 6-BIT REGISTER DIFFERENTIAL DATA CLOCK

6-BIT REGISTER
DIFFERENTIAL DATA CLOCK
SY10E451
SY100E451
FEATURES
s 1100MHz min. toggle frequency
s Extended 100E VEE range of –4.2V to –5.5V
s Differential inputs: data and clock
s VBB output for single-ended use
s Asynchronous Master Reset
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E451
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E451 offer six D-type flip-flops with single-
ended outputs and differential data and clock inputs,
designed for use in new, high-performance ECL systems.
The registers are triggered by the rising edge of the CLK
input.
A logic HIGH on the Master Reset (MR) input resets all
outputs to a logic LOW. The VBB output is provided for use
as a reference voltage for single-ended reception of ECL
signals to that device only. When used for this purpose, it
is recommended that VBB is decoupled to VCC via a 0.01µF
capacitor.
BLOCK DIAGRAM
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
CLK
CLK
MR
VBB
D
Q0
R
D
Q1
R
D
Q2
R
D
Q3
R
D
Q4
R
D
Q5
R
PIN CONFIGURATION
CLK
VBB
CLK
VEE
MR
NC
D0
25 24 23 22 21 20 19
26
18
27
17
28
TOP VIEW
16
1
PLCC
15
J28-1
2
14
3
13
4
12
5 6 7 8 9 10 11
Q5
Q4
VCC
Q3
VCCO
Q2
Q1
PIN NAMES
Pin
D0–D5
D0–D5
CLK
CLK
MR
VBB
Q0–Q5
VCCO
1
Function
+ Data Input
– Data Input
+ Clock Input
– Clock Input
Master Reset Input
VBB Output
Data Outputs
VCC to Output
Rev.: C
Amendment: /1
Issue Date: February, 1998