SY10E336 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 3-BIT REGISTERED BUS TRANSCEIVER

3-BIT REGISTERED
BUS TRANSCEIVER
SY10E336
SY100E336
FEATURES
s 25Ω cutoff bus output
s Extended 100E VEE range of –4.2V to –5.5V
s 50Ω receiver output
s Transmit and receive registers
s 1500ps max. clock to bus
s 1000ps max. clock to Q
s Internal edge slow-down capacitors on bus outputs
s Additional package ground pins
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E336
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E336 offer three bus transceivers with
both transmit and receive registers and are designed for
use in new, high-performance ECL systems. The bus
outputs (BUS0 - BUS2) are designed to drive a 25Ω bus.
The receive outputs (Q0 – Q2) are specified for 50Ω. The
bus outputs feature a normal logic HIGH level (VOH) and a
cutoff LOW level when at a logic LOW. At cutoff, the outputs
go to –2.0V and the output emitter-follower is “off”,
presenting a high impedance to the bus. The bus outputs
have edge slow-down capacitors.
The Transmit Enable pins (TEN) determine whether
current data is held in the transmit register or new data is
loaded from the A/B inputs. A logic LOW on both of the bus
enable inputs (BUSEN), when clocked through the register,
disables the bus outputs to –2.0V.
The receiver section clocks bus data into the receive
registers after gating with the Receive Enable (RXEN)
input.
All registers are clocked by rising edge of CLK1 or CLK2
(or both).
Additional grounding is provided through the ground
pins (GND) which should be connected to 0V. The GND
pins are not electrically connected to the chip.
PIN CONFIGURATION
BUSEN1
BUSEN2
RXEN
VEE
CLK1
CLK2
A0
25 24 23 22 21 20 19
26
18
27
17
28
TOP VIEW
16
1
PLCC
15
J28-1
2
14
3
13
4
12
5 6 7 8 9 10 11
GND
BUS2
VCC
Q1
VCCO
BUS1
GND
PIN NAMES
Pin
A0–A2
B0–B2
TEN1, 2
RXEN
BUSEN1, 2
CLK1, 2
BUS0–BUS2
Q0–Q2
VCCO
Function
Data Inputs A
Data Inputs B
Transmit Enable Inputs
Receive Enable Input
Bus Enable Inputs
Clock Inputs
25Ω Cutoff Bus Outputs
Receive Data Outputs
VCC to Output
Rev.: C
Amendment: /2
1
Issue Date: February, 1998