SY10E256_06 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 3-BIT 4:1 MUX-LATCH

Micrel, Inc.
3-BIT 4:1
MUX-LATCH
SY10E256
SY1^S0^YE¹⁰2⁰5^E6²⁵⁶
SY100E256
FEATURES
s 950ps max. data to output
s Extended 100E VEE range of –4.2V to –5.5V
s 850ps max. latch enable to output
s Separate select controls
s Differential outputs
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E256
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E256 offer three 4:1 multiplexers followed
by latches with differential outputs designed for use in new,
high-performance ECL systems. Separate Select controls
are provided for the leading 2:1 mux pairs (see block
diagram).
When the Latch Enable (LEN) is at a logic LOW, the latch
is transparent and output data is controlled by the multiplexer
select controls. A logic HIGH on LEN latches the outputs.
The Master Reset (MR) overrides all other controls to set
the Q outputs LOW.
BLOCK DIAGRAM
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL1A
SEL1B
SEL2
LEN
MR
D
Q0
E
Q0
NR
D
Q1
E
Q1
NR
D
Q2
E
Q2
NR
PIN NAMES
Pin
D0x–D2x
SEL1A, SEL1B
SEL2
LEN
MR
Q0, Q0–Q2, Q2
VCCO
Function
Parallel Data Inputs
First-stage Select Inputs
Second-stage Select Input
Latch Enable
Master Reset
Data Outputs
VCC to Output
M9999-032206
[e-mail] or [phone]
1
Rev.: G
Amendment: /0
Issue Date: March 2006