SY10E212 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 3-BIT SCANNABLE REGISTER

3-BIT SCANNABLE
REGISTER
SY10E212
SY100E212
FEATURES
s Scannable version E112 driver
s Extended 100E VEE range of –4.2V to –5.5V
s 1025ps max. CLK to Output
s Dual differential outputs
s Master Reset
s Internal 75KΩ input pull-down resistors
s Fully compatible with industry standard 10KH,
100K ECL levels
s Fully compatible with Motorola MC10E/100E212
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E212 are scannable registered ECL
drivers typically used as fan-out memory address drivers
for ECL cache driving. In a VLSI array-based CPU design,
use of the E212 allows the user to conserve array output
cell functionality and also output pins.
The input shift register is designed with control logic
which greatly facilitates its use in boundary scan
applications.
PIN CONFIGURATION
BLOCK DIAGRAM
D
Q
D2
D
Q
D1
D0
S-IN
LOAD
SHIFT
CLK
MR
D
Q
S-OUT
Q2b
Q2a
Q2a
Q2b
Q1b
Q1a
Q1a
Q1b
LOAD
CLK
D2
VEE
D1
D0
S-IN
25 24 23 22 21 20 19
26
18
27
17
28
TOP VIEW
16
1
PLCC
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q2b
Q2a
VCC
Q1b
Q1a
Q1b
Q1a
Q0b
Q0a
Q0a
Q0b
PIN NAMES
Pin
D0 – D2
S-IN
LOAD
SHIFT
CLK
MR
S-OUT
Q[0:2]a, Q[0:2]b
Q[0:2]a, Q[0:2]b
VCCO
Function
Data Inputs
Scan Input
LOAD/HOLD Control
Scan Control
Clock
Master Reset
Scan Output
True Outputs
Inverting Outputs
VCC to Output
Rev.: C Amendment: /1
1
Issue Date: February, 1998