SY10E175 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 9-BIT LATCH WITH PARITY

9-BIT LATCH
WITH PARITY
SY10E175
SY100E175
FEATURES
s 9-bit latch
s Extended 100E VEE range of –4.2V to –5.5V
s Parity detection/generation
s 800ps max. D to Output
s Reset
s Internal 75KΩ input pull-down resistors
s Fully compatible with Motorola MC10E/100E175
s Available in 28-pin PLCC package
BLOCK DIAGRAM
D0
D8
DQ
Q0
EN
R
bits
1–7
DQ
Q8
EN
R
DESCRIPTION
The SY10/100E175 are 9-bit latches. They also feature
a tenth latched output (ODDPAR) which is formed as the
odd parity of the nine data inputs (ODDPAR is HIGH if
an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by
using D8 as the parity-type select (L = even parity, H =
odd parity) and using ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a
logical high and makes the latch transparent when placed
at a logic low level.
PIN CONFIGURATION
D5
D4
D3
VEE
LEN
MR
D2
25 24 23 22 21 20 19
26
18
27
17
28
TOP VIEW
16
1
PLCC
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q6
Q5
VCC
Q4
Q3
VCCO
Q2
DQ
ODDPAR
EN
R
PIN NAMES
LEN
MR
Pin
Function
D0 – D8
Data Inputs
LEN
Latch Enable
MR
Master Reset
Q0 – Q8
Data Outputs
ODDPAR
Parity Output
VCCO
VCC to Output
Rev.: C
Amendment: /1
1
Issue Date: February, 1998