SY10E167 Datasheet, PDF (1/3 Pages) Micrel Semiconductor – 6-BIT 2:1 MUX-REGISTER

SY NERGY
SEMICONDUCTOR
6-BIT 2:1 MUX-REGISTER
SY10E167
SY1^S0^YE¹⁰1⁰6^E7¹⁶⁷
SY100E167
FEATURES
s 1000MHz min. operating frequency
s Extended 100E VEE range of –4.2V to –5.5V
s 800ps max. clock to output
s Single-ended outputs
s Asynchronous Master Reset
s Dual clocks
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s ESD protection of 2000V
s Fully compatible with Motorola MC10E/100E167
s Available in 28-pin PLCC package
BLOCK DIAGRAM
DESCRIPTION
The SY10/100E167 offer six 2:1 multiplexers followed
by D flip-flops with single-ended outputs, designed for use
in new, high-performance ECL systems. The Select (SEL)
control allows one of the two data inputs to the multiplexer
to pass through. The two external clock signals (CLK1,
CLK2) are gated through a logical OR operation before use
as control for the six flip-flops. The selected data are
transferred to the flip-flops on the rising edge of CLK1 or
CLK2 (or both).
The multiplexer operation is controlled by the Select
(SEL) signal which selects one of the two bits of input data
at each mux to be passed through.
When a logic HIGH is applied to the Master Reset (MR)
signal, it operates asychronously to take all outputs Q to a
logic LOW.
PIN CONFIGURATION
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
D5a
D5b
SEL
CLK1
CLK2
MR
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
© 1999 Micrel-Synergy
DQ
Q0
R
DQ
Q1
R
DQ
Q2
R
DQ
Q3
R
DQ
Q4
R
DQ
Q5
R
D5b
CLK1
CLK2
VEE
MR
SEL
D0a
25 24 23 22 21 20 19
26
18
27
17
28
16
TOP VIEW
1
PLCC
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q5
Q4
VCC
Q3
Q2
VCCO
Q1
PIN NAMES
Pin
D0a–D5a
D0b–D5b
SEL
CLK1, CLK2
MR
Q0–Q5
VCCO
5-127
Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs
VCC to Output
Rev.: C Amendment: /1
Issue Date: February, 1998