SY10E160 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 12-BIT PARITY GENERATOR/CHECKER

12-BIT PARITY
GENERATOR/CHECKER
SY10E160
SY100E160
FEATURES
s Provides odd-HIGH parity of 12 inputs
s Extended 100E VEE range of –4.2V to –5.5V
s Output register with Shift/Hold capability
s 900ps max. D to Q, /Q output
s Enable control
s Asynchronous Register Reset
s Differential outputs
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E160
s Available in 28-pin PLCC package
BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
EN
HOLD
S-IN
SHIFT
CLK1
CLK2
R
Q
Q
0
0
D
Y
MUX
MUX
1
1
Y
SEL
SEL
R
DESCRIPTION
The SY10/100E160 are high-speed, 12-bit parity
generator/checkers with differential outputs, for use in
new, high-performance ECL systems. The output Q takes
on a logic HIGH value only when an odd number of inputs
are at a logic HIGH. A logic HIGH on the enable input (EN)
forces the output Q to a logic LOW.
An additional feature of the E160 is the output register.
Two multiplexers and their associated signals control the
register input by providing the option of holding present
data, loading the new parity data or shifting external data
in. To hold the present data, the Hold signal (HOLD) must
be at a logic LOW level. If the HOLD signal is at a logic
HIGH, the data present at the Q output is passed through
the first multiplexer. Taking the Shift signal (SHIFT) to a
logic HIGH will shift the data at the S-IN pin into the output
register. If the SHIFT signal is at a logic LOW, the output
of the first multiplexer is then passed through to the register.
The register itself is clocked on the rising edge of CLK1
or CLK2 (or both). The presence of a logic HIGH on the
reset pin (R) forces the register output Y to a logic LOW.
PIN CONFIGURATION
D5
D6
D7
VEE
D8
D9
D10
25 24 23 22 21 20 19
26
18
27
17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q
Q
VCC
Y
Y
VCCO
NC
Rev.: D Amendment: /0
1
Issue Date: February, 1998