SY10E156 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 3-BIT 4:1 MUX-LATCH

3-BIT 4:1
MUX-LATCH
SY10E156
SY100E156
FEATURES
s 900ps max. D to output
s Extended 100E VEE range of –4.2V to –5.5V
s 800ps max. LEN to output
s Differential outputs
s Asynchronous Master Reset
s Dual latch enables
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E156
s Available in 28-pin PLCC package
BLOCK DIAGRAM
DESCRIPTION
The SY10/100E156 offer three 4:1 multiplexers followed
by latches with differential outputs, designed for use in
new, high-performance ECL systems. The two external
latch enable signals (LEN1 and LEN2) are gated through a
logical OR operation before use as control for the three
latches. When both LEN1 and LEN2 are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN1 or LEN2 (or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the Select
(SEL0, SEL1) signals which select one of the four bits of
input data at each mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
PIN CONFIGURATION
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL0
SEL1
LEN1
LEN2
MR
4:1
MUX
4:1
MUX
4:1
MUX
D
Q0
E
Q0
NR
D
Q1
E
Q1
NR
D
Q2
E
Q2
NR
SEL0
SEL1
MR
VEE
LEN1
LEN2
D1c
25 24 23 22 21 20 19
26
18
27
17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
VCCO
Q0
PIN NAMES
Pin
D0x–D2x
SEL0, SEL1
LEN1, LEN2
MR
Q0–Q2
Q0–Q2
VCCO
1
Function
Input Data
Select Inputs
Latch Enables
Master Reset
True Outputs
Inverted Outputs
VCC to Output
Rev.: C
Amendment: /1
Issue Date: February, 1998