SY10E143 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 9-BIT HOLD REGISTER

9-BIT HOLD
REGISTER
SY10E143
SY100E143
FEATURES
s 700MHz min. operating frequency
s Extended 100E VEE range of –4.2V to –5.5V
s 9 bits wide for byte-parity applications
s Asynchronous Master Reset
s Dual clocks
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75kΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E143
s Available in 28-pin PLCC package
BLOCK DIAGRAM
D
Q0
MUX
D0
R
D
Q1
D1
MUX
R
D
Q2
MUX
D2
R
D
Q3
MUX
D3
R
D
Q4
D4
MUX
R
D
Q5
MUX
D5
R
D
Q6
D6
MUX
R
D
Q7
D7
MUX
R
D
Q8
D8
MUX
R
SEL
CLK1
CLK2
MR
DESCRIPTION
The SY10/100E143 are high-speed 9-bit hold registers
designed for use in new, high-performance ECL systems.
The E143 can hold current data or load new data. The nine
inputs, D0-D8, accept parallel input data.
The SEL (Select) control pin serves to determine the
mode of operation; either HOLD or LOAD. The input data
has to meet the set-up time before being clocked into the
nine input registers on the rising edge of CLK1 or CLK2.
The MR (Master Reset) control signal asynchronously
resets all nine registers to a logic LOW when a logic HIGH
is applied to MR.
The E143 is designed for applications requiring high-
speed registers, pipeline registers, synchronous operation,
and is also suitable for byte-wide parity.
PIN CONFIGURATION
MR
CLK1
CLK2
VEE
NC
D0
D1
25 24 23 22 21 20 19
26
18
27
17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q7
Q6
VCC
Q5
VCCO
Q4
Q3
PIN NAMES
Pin
D0-D8
SEL
CLK1, CLK2
MR
Q0-Q8
NC
VCCO
1
Function
Parallel Data Inputs
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
No Connection
VCC to Output
Rev.: D Amendment: /0
Issue Date: August, 1998