SY10E142_06 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 9-BIT SHIFT REGISTER

Micrel, Inc.
9-BIT SHIFT
REGISTER
SY10E142
SY1^S0^YE¹⁰1⁰4^E2¹⁴²
SY100E142
FEATURES
s 700MHz min. shift frequency
s Extended 100E VEE range of –4.2V to –5.5V
s 9 bits wide for byte-parity applications
s Asynchronous Master Reset
s Dual clocks
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E142
s Available in 28-pin PLCC package
BLOCK DIAGRAM
S-IN
1
D0
0
1
D1
0
1
D2
0
1
D3
0
1
D4
0
1
D5
0
1
D6
0
1
D7
0
1
D8
0
SEL
CLK1
CLK2
MR
DQ
Q0
DQ
Q1
DQ
Q2
DQ
Q3
DQ
Q4
DQ
Q5
DQ
Q6
DQ
Q7
DQ
Q8
M9999-032006
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DESCRIPTION
The SY10/100E142 are high-speed 9-bit shift registers
designed for use in new, high-performance ECL systems.
The E142 can accept serial or parallel data to be shifted out
in one direction as both serial and parallel outputs. The
nine inputs, D0-D8, accept parallel input data, while S-IN
accepts serial input data.
The SEL (Select) control pin serves to determine the
mode of operation, either SHIFT or LOAD. The shift direction
is from bit 0 to bit 8. The input data has to meet the set-up
time before being clocked into the nine input registers on
the rising edge of CLK1 or CLK2. Shifting is also performed
on the rising edge of either CLK1 or CLK2. The MR (Master
Reset) control signal asynchronously resets all nine
registers to a logic LOW when a logic HIGH is applied to
MR.
The E142 is designed for applications such as diagnostic
scan registers, parallel-to-serial conversions and is also
suitable for byte-wide parity.
PIN NAMES
Pin
D0-D8
S-IN
SEL
CLK1, CLK2
MR
Q0-Q8
VCCO
Function
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
VCC to Output
Rev.: E
Amendment: /0
1
Issue Date: March 2006