SY10E116 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – QUINT DIFFERENTIAL LINE RECEIVER

QUINT DIFFERENTIAL
LINE RECEIVER
SY10E116
SY100E116
FEATURES
s 450ps max. Propagation Delay
s Extended 100E VEE range of –4.2V to –5.5V
s VBB output for single-ended reception
s Fully compatible with industry standard 10KH,
100K I/O levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E116
s Available in 28-pin PLCC package
BLOCK DIAGRAM
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
D4
Q4
VBB
PIN NAMES
Pin
D0, D0-D4, D4
Q0, Q0-Q4, Q4
VBB
VCCO
Function
Differential Input Pairs
Differential Output Pairs
Reference Voltage Output
VCC to Output
DESCRIPTION
The SY10/100E116 are quint differential line receivers
designed for use in new, high-performance ECL systems.
These devices have emitter-follower outputs and an
internally generated reference supply (VBB) for single-
ended reception.
Active current sources combined with Micrel-Synergy’s
ASSET™ technology provide the receivers with excellent
common mode noise rejection.
The receiver design features clamp circuitry to cause a
defined output state if both the inverting and non-inverting
inputs are left open; in this case the Q output goes LOW,
while the Q output goes HIGH.
If both inverting and non-inverting inputs are at equal
potential, the receiver does not go to a defined state, but
rather shares current in normal differential amplifier fashion,
producing output voltage levels midway between HIGH
and LOW.
The VBB output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using VBB for this purpose, it is
recommended that VBB is decoupled to VCC via a 0.01 µF
capacitor.
For higher bandwidth, please refer to the SY10/100E416
device.
PIN CONFIGURATION
D3
D2
D2
VEE
VBB
D0
D0
25 24 23 22 21 20 19
26
18
27
17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q3
Q3
VCC
Q2
Q2
VCCO
Q1
Rev.: E Amendment: /0
1
Issue Date: November, 1998