SY100S839V Datasheet, PDF (1/5 Pages) Micrel Semiconductor – ÷2/4, ÷4/5/6 CLOCK GENERATION CHIP

÷2/4, ÷4/5/6 CLOCK
GENERATION CHIP
ClockWorks™
SY100S839V
FINAL
FEATURES
s 3.3V and 5V power supply option
s 50ps output-to-output skew
s 50% duty cycle outputs
s Synchronous enable/disable
s Master Reset for synchronization
s Internal 75KΩ input pull-down resistors
s Available in 20-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
VCC Q0
Q0
Q1
Q1
Q2
Q2
Q3
20 19 18 17 16 15 14 13
Q3 VEE
12 11
TOP VIEW
SOIC
Z20-1
1
2
3
4
5
6
7
8
9 10
VCC EN
CLK CLK VBB MR VCC
TRUTH TABLE
CLK
/EN
Z
L
ZZ
H
X
X
NOTE:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
DIVSELa
0
1
MR
Function
L
Divide
L
Hold Q0–3
H
Reset Q0–3
Q0, Q1 OUTPUTS
Divide by 2
Divide by 4
DIVSELb1
0
0
1
1
DIVSELb0
0
1
0
1
Q2, Q3 OUTPUTS
Divide by 4
Divide by 6
Divide by 5
Divide by 5
DESCRIPTION
The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or, if
positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the VBB output, a sinusoidal
source can be AC-coupled into the device. If a single-
ended input is to be used, the VBB output should be
connected to the /CLK input and bypassed to ground via
a 0.01µF capacitor. The VBB output is designed to act as
the switching reference for the input of the S839V under
single-ended input conditions. As a result, this pin can
only source/sink up to 0.5mA of current.
The common enable (/EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input must be
asserted to ensure synchronization. For systems which
only use one S839V, the MR pin need not be exercised
as the internal divider designs ensures synchronization
between the ÷2/4, and the ÷4/5/6 outputs of a single
device.
PIN NAMES
Pin
CLK
/EN
MR
VBB
Q0, Q1
Q2, Q3
DIVSEL
1
Function
Differential Clock Inputs
Synchronous Enable
Master Reset
Reference Output
Differential ÷2/4 Outputs
Differential ÷4/5/6 Outputs
Frequency Select Input
Rev.: A
Amendment: /0
Issue Date: May, 1999