SY100S834 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – (÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8) CLOCK GENERATION CHIP

(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)
CLOCK GENERATION CHIP
ClockWorks™
SY100S834
SY100S834L
FEATURES
s 3.3V and 5V power supply options
s 50ps output-to-output skew
s Synchronous enable/disable
s Master Reset for synchronization
s Internal 75KΩ input pull-down resistors
s Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
Q0 ¹
Q0 2
VCC 3
Q1 4
Q1 ⁵
VCC 6
Q2 7
Q2 8
Q
÷1 or ÷2
R
Q
÷2 or ÷4
R
Q
÷4 or ÷8
R
QD
R
16 _VCC
15 _EN
14 _FSEL
13 _CLK
12 _CLK
11 VBB
10 MR
9 _VEE
SOIC
TOP VIEW
PIN NAMES
Pin
CLK
FSEL
EN
MR
VBB
Q0
Q1
Q2
Function
Differential Clock Inputs
Function Select
Synchronous Enable
Master Reset
Reference Output
Differential ÷1 or ÷2 Outputs
Differential ÷2 or ÷4 Outputs
Differential ÷4 or ÷8 Outputs
DESCRIPTION
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,
÷4, ÷8) clock generation chip designed explicitly for low
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
be driven by either a differential or single-ended ECL or,
if positive power supplies are used, PECL input signal.
In addition, by using the VBB output, a sinusoidal source
can be AC-coupled into the device. If a single-ended
input is to be used, the VBB output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
can only source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input
is LOW, SY100S834/L functions as a divide by 2, by 4
and by 8 clock generation chip. However, if FSEL input
is HIGH, it functions as a divide by 1, by 2 and by 4
clock generation chip. This latter feature will increase
the clock frequency by two folds.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
TRUTH TABLE
CLK
EN
Z
L
ZZ
H
X
X
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
FSEL
Q0 Outputs
L
Divide by 2
H
Divide by 1
1
MR
Function
L
Divide
L
Hold Q0–2
H
Reset Q0–2
Q1 Outputs
Divide by 4
Divide by 2
Q2 Outputs
Divide by 8
Divide by 4
Rev.: F Amendment: /0
Issue Date: September, 1999