SY100S811 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL

SINGLE SUPPLY 1:9
PECL/TTL-TO-PECL
ClockWorks™
SY100S811
FEATURES
s PECL version of popular ECLinPS E111
s Low skew
s Guaranteed skew spec
s VBB output
s TTL enable input
s Selectable TTL or PECL clock input
s Single +5V supply
s Differential internal design
s Similar pin configuration to E111
s PECL I/O fully compatible with industry standard
s Internal 75KΩ PECL input pull-down resistors
s Available in 28-pin PLCC and SOIC packages
BLOCK DIAGRAM
Q0
Q0
Q1
EIN
Q1
EIN
0
Q2
Q2
Q3
TIN
1
Q3
Q4
Q4
TEN
Q5
Q5
Q6
Q6
Q7
Q7
Q8
VBB
Q8
DESCRIPTION
The SY100S811 is a low skew 1-to-9 PECL differential
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin TEN.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S811 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
to maintain minimum skew.
The VBB output is intended for use as a reference
voltage for single-ended reception of PECL signals to that
device only. When using VBB for this purpose, it is
recommended that VBB is decoupled to VCC via a 0.01µF
capacitor.
PIN CONFIGURATION
VEE
TEN
EIN
VCC
EIN
VBB
TIN
25 24 23 22 21 20 19
26
18
27
17
28
TOP VIEW
16
1
PLCC
15
J28-1
2
14
3
13
4
12
5 6 7 8 9 10 11
Q3
Q3
Q4
VCCO
Q4
Q5
Q5
Rev.: F Amendment: /0
1
Issue Date: October, 1998