SY100S370 Datasheet, PDF (1/7 Pages) Micrel Semiconductor – UNIVERSAL DEMULTIPLEXER/ DECODER

UNIVERSAL
DEMULTIPLEXER/
DECODER
SY100S370
FEATURES
DESCRIPTION
s Max. propagation delay of 1200ps
s IEE min. of –92mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 60% faster than National or Signetics
s Approximately 40% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S370 is a universal demultiplexer/decoder
that can be used as either a dual 1-of-4 decoder or as a
single 1-of-8 decoder and is designed for use in high-
performance ECL systems. The Mode control (M) input
determines the function. In the dual 1-of-4 mode, each 4-
input group has a pair of active-LOW Enable (E) inputs.
The Enable pins are assigned such that in the single 1-of-
8 mode they can be tied together in pairs to result in two
active-LOW Enable inputs. E1a will be tied to E1b and E2a
to E2b.
The auxiliary inputs (Hn) are used to determine whether
the outputs are active-HIGH or active-LOW. The address
inputs for the dual 1-of-4 mode are A0a, A1a, A0b. A2a is
unused. In the 1-of-8 mode, the address inputs are A0a,
A1a, A2a. The inputs on the device have 75KΩ pull-down
resistors.
PIN CONFIGURATIONS
PIN NAMES
Pin
Ana, Anb
Ena, Enb
M
Ha
Hb
Hc
Z0 – Z7
Zna, Znb
VEES
VCCA
Function
Address Inputs (n = 0,1,2)
Enable Inputs (n = 1,2)
Mode Control Input
Z0 – Z3 (Z0a – Z3a) Polarity Select Input
Z4 – Z7 (Z0b – Z3b) Polarity Select Input
Common Polarity Select Input
Single 1-of-8 Data Outputs
Dual 1-of-4 Data Outputs (n = 1...4)
VEE Substrate
VCCO for ECL Outputs
E1a
E1b
VEE
VEES
E2b
E2a
Ha
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
1
16
J28-1
28
17
27
18
26
19 20 21 22 23 24 25
Z0a (Z0)
Z3a (Z3)
VCCA
VCC
VCC
Z1b (Z5)
Z2b (Z6)
Hc
Hb
A0b
A1b
Z3b (Z7)
Z0b (Z4)
24 23 22 21 20 19
1
18
2
17
3
Top View 16
4
Flatpack
F24-1
15
5
14
6
13
7 8 9 10 11 12
A2a
M
A1a
A0a
Z1a (Z1)
Z2a (Z2)
Rev.: G Amendment: /0
1
Issue Date: July, 1999