SY100S360_06 Datasheet, PDF (1/6 Pages) Micrel Semiconductor – DUAL PARITY CHECKER/GENERATOR

Micrel, Inc.
DUAL PARITY
CHECKER/
GENERATOR
SY100S360
SY100S360
FEATURES
DESCRIPTION
s Max. propagation delay of 2200ps
s IEE min. of –70mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 15% faster than Fairchild 300K
s Approximately 30% lower power than Fairchild 300K
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S360 is a dual parity checker/generator and
is designed for use in high-performance ECL systems. The
inputs are segmented into two groups of nine inputs each
and the parity output is at a logic LOW when an even
number of inputs are at a logic HIGH. In each group, one of
the nine inputs (Ia, Ib) has a shorter propagation delay and,
therefore, is ideal as the expansion input for parity
generation of wider data.
A Compare output (C) is also provided which allows
comparison of two 8-bit words. A logic LOW on the C output
indicates a match. The inputs on this device have 75KΩ
pull-down resistors.
BLOCK DIAGRAM
I0a
I1a
I2a
I3a
Za
I4a
I5a
I6a
I7a
Ia
C
I0b
I1b
I2b
I3b
I4b
I5b
Zb
I6b
I7b
Ib
M9999-032406
[e-mail] or [phone]
1
Rev.: H Amendment: /0
Issue Date: March 2006