SY100S360 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – DUAL PARITY CHECKER/ GENERATOR

DUAL PARITY
CHECKER/
GENERATOR
SY100S360
FEATURES
DESCRIPTION
s Max. propagation delay of 2200ps
s IEE min. of –70mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 15% faster than Fairchild 300K
s Approximately 30% lower power than Fairchild 300K
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S360 is a dual parity checker/generator and
is designed for use in high-performance ECL systems. The
inputs are segmented into two groups of nine inputs each
and the parity output is at a logic LOW when an even
number of inputs are at a logic HIGH. In each group, one of
the nine inputs (Ia, Ib) has a shorter propagation delay and,
therefore, is ideal as the expansion input for parity
generation of wider data.
A Compare output (C) is also provided which allows
comparison of two 8-bit words. A logic LOW on the C output
indicates a match. The inputs on this device have 75KΩ
pull-down resistors.
PIN CONFIGURATIONS
BLOCK DIAGRAM
I0a
I1a
I2a
I3a
I4a
I5a
I6a
I7a
Ia
I0b
I1b
I2b
I3b
I4b
I5b
I6b
I7b
Ib
11 10 9 8 7 6 5
I6a 12
4 Ia
I7a 13
3
Za
VEE 14
VEES 15
I0b 16
Top View
PLCC
J28-1
2
VCCA
1
VCC
28
VCC
I1b 17
27 C
I2b 18
26 Zb
Za
19 20 21 22 23 24 25
24 23 22 21 20 19
I3b
1
18
I5a
I4b
2
17
I4a
C
I5b
3
I6b
4
Top View 16 I3a
Flatpack
F24-1
15
I2a
I7b
5
14
I1a
Ib 6
13
I0a
7 8 9 10 11 12
Zb
Rev.: G Amendment: /0
1
Issue Date: July, 1999