SY100S351 Datasheet, PDF (1/7 Pages) Micrel Semiconductor – HEX D FLIP-FLOP

HEX D FLIP-FLOP
SY100S351
FEATURES
DESCRIPTION
s Max. toggle frequency of 700MHz
s Clock to Q max. of 1200ps
s IEE min. of –98mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 50% faster than Fairchild 300K
s Better than 20% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
D5
DQ
Q5
CPb
CPa
ER Q
Q5
MR
D4
DQ
Q4
ER Q
Q4
D3
DQ
Q3
ER Q
Q3
The SY100S351 offers six D-type, edge-triggered,
master/slave flip-flops with differential outputs, and is
designed for use in high-performance ECL systems. The
flip-flops are controlled by the signal from the logical OR
operation on a pair of common clock signals (CPa, CPb).
Data enters the master when both CPa and CPb are LOW
and transfers to the slave when either CPa or CPb (or both)
go to a logic HIGH. The Master Reset (MR) input overrides
all other inputs and takes the Q outputs to a logic LOW. The
inputs on this device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
D2
D3
VEE
VEES
MR
CPa
CPb
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
1
16
J28-1
28
17
27
18
26
19 20 21 22 23 24 25
Q2
Q2
VCCA
VCC
VCC
Q3
Q3
24 23 22 21 20 19
D4 1
18 D1
D5 2
17 D0
Q5 3
Q5 4
Q4 5
Top View 16 Q0
Flatpack
F24-1
15
Q0
14 Q1
Q4 6
13 Q1
7 8 9 10 11 12
D2
DQ
Q2
ER Q
Q2
D1
DQ
Q1
ER Q
Q1
D0
DQ
Q0
ER Q
Q0
Rev.: G Amendment: /0
1
Issue Date: July, 1999