SY100S350 Datasheet, PDF (1/7 Pages) Micrel Semiconductor – HEX D-LATCH

HEX D-LATCH
SY100S350
FEATURES
DESCRIPTION
s Max. transparent propagation delay of 900ps
s Min. Master Reset and Enable pulse widths of 100ps
s IEE min. of –98mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s More than 40% faster than Fairchild
s Approximately 30% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S350 offers six high-speed D-Latches with
both true and complement outputs, and is performance
compatible for use with high-performance ECL systems.
When both enable signals (Ea and Eb) are at a logic LOW,
the latches are transparent and the input signals( D0–D5)
appear at the outputs (Q0–Q5) after a propagation delay. If
either or both of the enable signals are at a logic HIGH, then
the latches store the last valid data present on its inputs
before Ea or Eb went to a logic HIGH. The Master Reset
(MR) overrides all other input signals and takes the outputs
to a logic LOW state. All inputs have 75KΩ pull-down
resistors.
PIN CONFIGURATIONS
BLOCK DIAGRAM
D5
D
Q5
Eb
Ea
ER
Q5
MR
D4
D
Q4
ER
Q4
D3
D
Q3
ER
Q3
D2
D
Q2
ER
Q2
D1
D
Q1
ER
Q1
D0
D
Q0
ER
Q0
D2
D3
VEE
VEES
MR
Ea
Eb
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
1
16
J28-1
28
17
27
18
26
19 20 21 22 23 24 25
Q2
Q2
VCCA
VCC
VCC
Q3
Q3
24 23 22 21 20 19
D4 1
18
D1
D5 2
17
D0
Q5 3
Q5 4
Q4 5
Top View 16 Q0
Flatpack
F24-1
15
Q0
14
Q1
Q4 6
13
Q1
7 8 9 10 11 12
Rev.: G Amendment: /0
1
Issue Date: July, 1999