SY100S336 Datasheet, PDF (1/9 Pages) Micrel Semiconductor – 4-STAGE COUNTER/ SHIFT REGISTER

4-STAGE COUNTER/
SHIFT REGISTER
SY100S336
FEATURES
DESCRIPTION
s Max. shift frequency of 700MHz
s Clock to Q delay max. of 1100ps
s IEE min. of –170mA
s Internal 75KΩ input pull-down resistors
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s 50% faster than Fairchild 300K at lower power
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
PIN CONFIGURATIONS
P0
CP
VEE
VEES
MR
S0
S1
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
1
J28-1
16
28
17
27
18
26
19 20 21 22 23 24 25
Q2
Q2
VCCA
VCC
VCC
Q1
Q1
24 23 22 21 20 19
S2 1
18
P1
CEP 2
17
P2
D0/CET 3
TC 4
Q0 5
Top View 16 P3
Flatpack
F24-1
15
D3
14
Q3
Q0 6
13
Q3
7 8 9 10 11 12
The SY100S336 functions either as a modulo-16 up/
down counter or as a 4-bit bidirectional shift register and is
designed for use in high-performance ECL systems. Three
Select inputs (Sn) are provided for determining the mode of
operation. The Function Table lists the available modes of
operation. In order to allow cascading for multistage
counters, two Count Enable controls (CEP, CET) are
provided. The CET input also functions as the Serial Data
input (S0) for a shift-up operation, while the D3 input serves
as the Serial Data input for the shift-down operation.
When the device is in the counting mode, the Terminal
Count (TC) goes to a logical LOW when the count reaches
15 for count-up or reaches 0 for count-down. When in the
shift mode, the TC output simply repeats the Q3 output.
The flexiblity provided by the TC/Q3 output and the D0/
CET input allows these signals to be interconnected from
one stage to the next higher stage for multistage counting
or shift-up operations. The individual Presets (Pn) allow
initialization of the counter by entering data in parallel to
preset the counter. A logic HIGH on the Master Reset (MR)
overrides all other inputs and asynchronously clears the
flip-flops. An additional synchronous Clear is provided, as
well as a complement function which synchronously inverts
the contents of the flip-flops. All inputs have 75KΩ pull-
down resistors.
PIN NAMES
Pin
CP
CEP
D0/CET
S0 — S2
MR
VEES
VCCA
P0 – P3
D3
TC
Q0 — Q3
Q0 — Q3
Function
Clock Pulse Input
Count Enable Parallel Input (Active LOW)
Serial Data Input/Count Enable Trickle
Input (Active LOW)
Select Inputs
Master Reset Input
VEE Substrate
VCCO for ECL Outputs
Preset Inputs
Serial Data Input
Terminal Count Output
Data Outputs
Complementary Data Outputs
Rev.: G Amendment: /0
1
Issue Date: July, 1999