SY100S331 Datasheet, PDF (1/7 Pages) Micrel Semiconductor – TRIPLE D FLIP-FLOP

TRIPLE D
FLIP-FLOP
SY100S331
FEATURES
DESCRIPTION
s Max. toggle frequency of 800MHz
s Differential outputs
s IEE min. of –80mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 150% faster than Fairchild
s 40% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CPc), as well as
its own clock pulse (CPn). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CPc
and CPn are LOW and enters the slave on the rising edge
of either CPc or CPn (or both).
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SDn) and Direct Clear (CDn) signals. The MR,
MS, SDn and DCn signals override the clock signals. The
inputs on this device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
BLOCK DIAGRAM
CD2
CD
CPC
CP2
CP
Q2
D2
D _SD
Q2
SD2
CD1
CD
CP1
CP
Q1
D1
D _SD
Q1
SD1
CD0
CD
CP0
CP
Q0
D0
D _SD
Q0
SD0
MS
CPC
VEE
VEES
MR
SD1
D1
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
1
16
J28-1
28
17
27
18
26
19 20 21 22 23 24 25
Q1
Q1
VCCA
VCC
VCC
Q2
Q2
24 23 22 21 20 19
CP1 1
18 SD0
CD1 2
17 CD0
SD2 3
CD2 4
CP2 5
Top View 16 CP0
Flatpack
F24-1
15
D0
14 Q0
D2 6
13 Q0
7 8 9 10 11 12
MS MR
Rev.: G Amendment: /0
1
Issue Date: July, 1999