SY100S325 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – LOW-POWER HEX ECL-to-TTL TRANSLATOR

LOW-POWER HEX
ECL-to-TTL
TRANSLATOR
SY100S325
FEATURES
DESCRIPTION
s Max. propagation delay of 3.7ns
s IEE min. of –37mA
s TTL outputs
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s 25% faster than National's 325
s Differential inputs with built-in offset
s Voltage and temperature compensation for improved
noise immunity
s VBB output for single-ended use
s Internal 75KΩ input pull-down resistors
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S325 are hex translators for converting
100K ECL logic levels to TTL logic levels. Inputs can be
used as inverting, non-inverting or differential receivers.
An internal reference voltage generator provides VBB for
single-ended operation or for use in Schmitt trigger
applications. All inputs have 75KΩ pull-down resistors.
The outputs will go LOW when the inputs are either open
or have the same potential.
When used in single-ended operation, the apparent
input threshold of the true inputs is 20mV to 40mV higher
(positive) than the threshold of the complementary inputs.
The VTTL and VEE power may be applied in either order.
PIN CONFIGURATIONS
BLOCK DIAGRAM
VBB
D0
Q0
D0
D1
Q1
D1
D2
Q2
D2
D3
Q3
D3
D4
Q4
D4
D5
Q5
D5
VTTL
VTTL
VCC
VCC
VCC
Q2
Q1
25 24 23 22 21 20 19
26
18
27
17
28
16
1
Top View
15
PLCC
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
D4
D3
D3
VEES
VEE
VBB
D2
24 23 22 21 20 19
D4
1
18
D2
D5
2
17
D1
D5
3
Q5
4
Q4
5
Q3
6
Top View
Flatpack
F24-1
16
D1
15
D0
14
D0
13
Q0
7 8 9 10 11 12
PIN NAMES
Pin
D0–D5
D0–D5
Q0–Q5
VEES
VTTL
VCCA
Function
Data Inputs
Inverting Data Inputs
Data Outputs
VEE Substrate
TTL VCC Power Supply
VCCO for ECL Outputs
Rev.: F
Amendment: /0
1
Issue Date: July, 1999