SY100S324 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – LOW POWER HEX TTL-to-ECL TRANSLATOR

LOW POWER HEX
TTL-to-ECL
TRANSLATOR
SY100S324
FEATURES
DESCRIPTION
s Max. propagation delay of 1.4ns
s IEE min. of –70mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Differential outputs
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s Twice as fast as Fairchild’s 324
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S324 is a hex translator designed to convert
TTL logic levels to 100K ECL levels. The inputs are TTL
compatible with differential outputs that can either be
used as an inverting/non-inverting translator or as
differential line drivers. A common Enable (E), when LOW,
holds all inverting outputs HIGH and holds all non-
inverting outputs LOW.
When used in the differential mode, due to its high
common mode rejection, it overcomes voltage gradients
between the TTL and ECL ground systems. The VEE and
VTTL power may be applied in either order.
PIN CONFIGURATIONS
BLOCK DIAGRAM
E
Q0
D0
Q0
Q1
D1
Q1
Q2
D2
Q2
Q3
D3
Q3
Q4
D4
Q4
Q5
D5
Q5
Q2
Q2
VCC
VCC
VCCA
VCCA
Q3
25 24 23 22 21 20 19
26
18
27
17
28
16
1
Top View
15
PLCC
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
D0
VTTL
E
VEES
VEE
D3
D4
24 23 22 21 20 19
D1
1
18
D5
D2
2
17
Q5
Q0
3
Q0
4
Q1
5
Q1
6
Top View
Flatpack
F24-1
16
Q5
15
Q4
14
Q4
13
Q3
7 8 9 10 11 12
PIN NAMES
Pin
D0–D5
E
Q0–Q5
Q0–Q5
VEES
VTTL
VCCA
1
Function
Data Inputs
Enable Inputs
Data Outputs
Complementary Data Outputs
VEE Substrate
TTL VCC Power Supply
VCCO for ECL Outputs
Rev.: F
Amendment: /0
Issue Date: July, 1999