SY100S317 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – TRIPLE 2-WIDE OA/OAI GATE

TRIPLE 2-WIDE
OA/OAI GATE
SY100S317
FEATURES
DESCRIPTION
s Max. propagation delay of 900ps
s IEE min. of –48mA
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s Approximately 40% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
Ea
The SY100S317 is a set of ultra-fast, triple 2-wide OR/
AND gates designed for use in high-performance ECL
systems. This device offers both true and complement
outputs. The inputs on this device have 75KΩ pull-down
resistors.
PIN CONFIGURATIONS
Ea
Eb
VEE
VEES
Ec
D1b
D2b
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
1
16
J28-1
28
17
27
18
26
19 20 21 22 23 24 25
Ob
Ob
VCCA
VCC
VCC
Oc
Oc
D1a
D2a
Oa
D3a
Oa
24 23 22 21 20 19
D4a
D3b
1
18
D4a
D4b
2
17
D3a
Eb
D1c
3
Top View 16 D2a
D1b
D2c
4
Flatpack
F24-1
15
D1a
D3c
5
14
Oa
D2b
Ob
D4c
6
13
Oa
D3b
Ob
7 8 9 10 11 12
D4b
Ec
D1c
D2c
Oc
D3c
Oc
PIN NAMES
D4c
Pin
Function
Dna – Dnc
Data Inputs (n = 1...4)
Ea – Ec
Enable Inputs
Oa – Oc
Data Outputs
Oa – Oc
Complementary Data Outputs
VEES
VEE Substrate
VCCA
VCCO for ECL Outputs
Rev.: G Amendment: /0
1
Issue Date: July, 1999