SY100S314 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – QUINT DIFFERENTIAL LINE RECEIVER

QUINT DIFFERENTIAL
LINE RECEIVER
SY100S314
FEATURES
DESCRIPTION
s Max. propagation delay of 900ps
s Differential outputs
s IEE min. of –60mA
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s VBB output for single-ended use
s More than twice as fast as Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S314 offers five differential line receivers
with emitter follower outputs, designed for use in high-
performance ECL systems. For single-ended operation,
the VBB reference voltage is available. In the single-ended
mode, the apparent input threshold of the true inputs is
30mV higher than the threshold of the complementary
inputs.
Common mode rejection of +1.0V is achieved through
the use of active current sources. If both the true and
complement inputs are at the same potential between VEE
and VCC, then the complementary outputs will take on a
logic HIGH state. Unlike the other members of the Synergy
300K family, the inputs on this device do not have pull-
down resistors.
PIN CONFIGURATIONS
BLOCK DIAGRAM
Da
Da
Db
Db
Dc
Dc
Dd
Dd
De
De
PIN NAMES
Oa
Oa
Ob
Ob
Oc
Oc
Od
Od
Oe
Oe
VBB
Db
Db
VEE
VEES
VBB
Dc
Dc
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
1
J28-1
16
28
17
27
18
26
19 20 21 22 23 24 25
Oc
Oc
VCCA
VCC
VCC
Od
Od
24 23 22 21 20 19
Dd 1
18
Da
Dd 2
17
Da
De 3
De 4
Oe 5
Top View 16 Oa
Flatpack
F24-1
15
Oa
14
Ob
Oe 6
13
Ob
7 8 9 10 11 12
Pin
Da – De
Da – De
Oa – Oe
Oa – Oe
VEES
VCCA
Function
Data Inputs
Inverting Data Inputs
Data Outputs
Complementary Data Outputs
VEE Substrate
VCCO for ECL Outputs
1
Rev.: G Amendment: /0
Issue Date: July, 1999